How can we use TVM to generate code for FPGA-based accelerators?


#1

As we know, the TVM compiler stack can also be used for deep learning accelerators based on FPGAs, which also have lots of appliction scenerios. But FPGA-based accelerators may have created its own instruction set and architechture, so my question is , based on this, in order to use the compiler stack to generate schedule code for such an accelerator, what is needed to be done and how to do it ? Is there any examples or tutorials that demonstrate this ? Any advice or suggestions will be appreciated.
Big thanks!


#2

Just adding some side details to this, since I too have the same issue as well. But to add to this, I have some C++ functions that perform the functionality required from the accelerator. I would like to know from where I can start adding a python like interface for TVM to use this accelerator? Sorry if I am missing something here. Thanks in advance

Update: --> I am not sure if this is right but there is an extensions example in the tvm repo in tvm/apps/extensions. Maybe this seems like a right example to look at ?


#3

Hi Eddie,

One approach is to use a runtime to serve as an intermediate layer between TVM and your accelerator. The runtime can expose a C API which TVM calls into once it’s lowered. The C runtime can then generate assembly on the fly in a JIT fashion.

I will point you to some examples once we have our alpha release. @slahiruk, let me know if you also would like alpha access to some FPGA examples.

Thierry


#4

Sure I would like to have access to some of the FPGA examples in the alpha release (That would be nice). Thanks!


#5

I also want to access the FPGA examples.


#6

Hi Thierry,
That would be nice! @thierry So when can we have access to your alpha release? I have already PM you my github ID, Please check! Thanks all the time!


#7

Hi Eddie, sorry we’ve been making changes to the repo and need to make sure tests are stable first. I’ll notify you when you’ll be receiving access.